This invention relates to programmable memory devices of the kind that can be programmed as well as erased by electrical means, and particularly to improvements in such devices of the kind employing a floating gate MOS structure.
Metal-oxide-semiconductor (MOS) memory devices are known which are constructed with an electrically isolated floating gate between the control gate and the semiconductive body. By inducing a high enough electric field of the proper polarity between the floating gate and the semiconductive body, charge carriers can tunnel through a thin insulator from the semiconductive body to the floating gate to program the device to one binary state. By inducing an electric field of the opposite polarity between the floating gate and the semiconductive body, charge carriers can be removed from the floating gate to erase the data or cause the device to revert to its other binary state.
An electrically erasable programmable read-only memory (EEPROM) of the MOS kind employing a floating gate and a tunneling oxide is disclosed in U.S. Pat. No. 4,203,158. Since the floating gate in this type of device is electrically isolated from the outside, the programming and erase voltage is applied between the accessible control gate and the substrate, and the tunneling electric field is induced between the floating gate and the substrate through capacitive coupling. There are two capacitances associated with the floating gate. One is the capacitance between the floating gate and the substrate, and the other is the capacitance between the floating gate and the control gate. These two capacitances form a voltage divider across which the applied voltage divides inversely as the capacitances.
In order to provide effective tunneling action with reasonably low supply voltage in the neighborhood of 20 volts, the tunneling oxide between the floating gate and the substrate must be very thin, for example about 100 angstroms or less and about one-tenth the thickness of the oxide between the floating gate and the control gate. If the two gates were of the same area, most of the induced electric field would be developed across the thicker inter-gate oxide and very little electric field would appear across the tunneling oxide where it is needed. For effective tunneling action in the program mode, the overlap area between the control gate and the floating gate must be very large relative to the tunneling area. For the example given above, the overlap area must be about 15 times the area of the tunneling oxide. This large area requirement makes it rather difficult to fabricate high density EEPROMS that have a capacity of more than 16K bits and yet are not unduly bulky. There is a great need for a new EEPROM design of reduced physical size which also can be programmed and erased with relatively low voltages currently in use.